1. Field of the Invention
The present invention relates to a method of making a metal oxide semiconductor field effect transistor, and more particularly to a method of making metal oxide semiconductor field effect transistor with a lightly doped drain structure. The metal oxide semiconductor field effect transistor with a lightly doped drain structure according to the present invention avoids a generation of hot electrons due to a high electric field formed at edge portions of its gate electrode, thereby improving its life time and reliability.
2. Description of the Prior Art
Referring to FIGS. 8A to 8C, there is illustrated a conventional method of making a metal oxide semiconductor field effect transistor (MOSFET) with a lightly doped drain (LDD) structure.
On a P type semiconductor substrate 11, first, field regions 12 are formed to isolate adjacent cells from one another, as shown in FIG. 8A. Impurity ions for providing an electrical characteristic of MOSFET to be made are implanted in a portion of the surface of P type semiconductor substrate 11 corresponding to each active region located between adjacent field regions 12. Thereafter, a gate insulating film 13 is formed over the entire surface of P type semiconductor substrate 11 including the field regions 12. On the gate insulating film 13, a gate electrode 14 having a certain width is formed within each active region. The exposed surface of gate electrode 14 is subjected to an oxidization, thereby forming a gate cap insulating film 15. Over the entire exposed surface, a semiconductor layer 16 with a certain thickness is formed to provide gate side wall spacers.
Subsequently, the semiconductor layer 16 is subjected to an anisotropic etching using a reactive ion etching (RIE) method, thereby forming gate side wall semiconductor layers 17 at side walls of the gate electrode 14, respectively, as shown in FIG. 8B. At this time, the gate cap insulating film 15 formed on the surface of gate electrode 14 serves as an etch stopper. By using the gate cap insulating film 15 and gate side wall semiconductor layers 17 as a mask, N.sup.+ type (namely, high concentration) impurity ions are then implanted in a portion of the surface of P type semiconductor substrate 11 corresponding to the active region. According to a diffusion of the impurity ions, N.sup.+ type source and drain regions 18 and 18a are formed.
Thereafter, gate side wall semiconductor layers 17 are removed, as shown in FIG. 8C. By using the gate cap insulating film 15 as a mask, N.sup.- type (namely, low concentration) impurity ions are then implanted in a portion of the surface of P type semiconductor substrate 11 corresponding to the active region. According to a diffusion of the impurity ions, N.sup.- type source and drain regions 19 and 19a are formed.
Thus, the source/drain regions form a LDD structure comprising low and high concentration regions,
Now, an operation of the MOSFET made by the prior art will now be described, in conjunction with FIG. 9.
As a gate bias voltage V.sub.G (about 3.3 V) is applied to the gate electrode 14, a drain voltage V.sub.D (about 3.3 V) to the N.sup.+ drain region 18a and N.sup.- drain region 19a, and a minus substrate voltage V.sub.S to the P type semiconductor substrate 11, an inversion layer and a depletion layer are formed. In the N.sup.- type source region 19, electrons are generated which, turns, strike a lattice in N.sup.- type drain region 19a, thereby causing a generation of holes and electrons.
At this time, the generated electrons are injected into the N.sup.- type drain region 19a to which the plus voltage of about 3.3 V has been applied. However, the generated holes are moved to three regions. That is, the holes are not only trapped into the gate electrode 14 and the gate insulating film 13, but also often moved to the P type semiconductor substrate 11. The holes trapped in the gate electrode 14 may affect the overall circuit, but hardly have an effect on the operation of MOSFET. The holes moved to the P type semiconductor substrate 11 also have no effect on the operation of MOSFET, since they disappear in the P type semiconductor substrate 11. However, the holes trapped in the gate insulating film 13 cause the MOSFET to be turned on before the predetermined bias voltage V.sub.G of about 3.3 V is applied to the gate electrode 14.
As a result, the characteristic of MOSFET in operation and the reliability of a finally obtained element are reduced. Upon trapping of holes into the gate insulating film 13, furthermore, a defect may occur at the gate insulating film 13, thereby causing the performance of the element to be deteriorated and the life thereof to be shortened. Such holes are referred to as hot carriers and a phenomenon caused thereby is referred to as a hot carrier effect.
The prior aft also has a problem of an increase resistance, since the source/drain regions are constituted by N.sup.+ type and N.sup.- type regions. In addition, it is impossible to obtain source/drain regions having desired accurate widths, due to the difficulty of accurately controlling the thickness of the gate side wall semiconductor layers. Consequently, a short channel effect is caused.